I will review your pcb design, fix drc and erc errors and prepare jlcpcb gerbers
PCB Design, Circuit Design, Embedded and IoT, KiCad, EasyEDA,Firmware, ESP32
About this Gig
Is your board failing DRC, using a doubtful stackup, or relying on parts that are out of stock? I review your design and bring it to a manufacturable state.
A RECENT EXAMPLE
On a 4-layer power distribution board I took the design from 263 DRC violations and 17 ERC errors to zero errors. I corrected a 4.67 mm stackup to the standard 1.6 mm, opened solder mask for planned rework, checked trace width and creepage against IPC-2221, replaced obsolete parts and prepared the Gerbers, BOM and placement file for JLCPCB.
WHAT I CHECK
- ERC and DRC errors, unconnected nets, clearance and annular ring issues
- Stackup, copper weight and solder mask settings
- Footprint and part availability (LCSC/JLCPCB stock)
- Trace width and creepage for high-current or high-voltage nets
- Reference designators and schematic-to-PCB sync
TOOLS
KiCad and EasyEDA exports. Send your project files and your target fab.
TO START
Message me with your files and what you need. I reply with the scope and a timeline.
Specialization:
Schematics
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Layout
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Footprint
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Analysis
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Gerber
File format:
Gerber
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SCH
•
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Other
Software:
EasyEDA
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Fusion 360
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KiCad
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LTspice
Interface:
HDMI
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MIPI DSI/CSI
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I2S
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UART
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USB
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SPI
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I2C
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Wi-Fi
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BT
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GSM/GPRS
My Portfolio
FAQ
Do you redesign my board?
This gig is a review and correction. A full redesign is a separate order.
Which formats can you open?
KiCad and EasyEDA projects, plus Gerbers for review.
Will it pass JLCPCB checks?
I check against JLCPCB's standard manufacturing limits and prepare the files. Final acceptance is decided by the fab.

