I will do uvm simulation using systemverilog for complex hdl module or soc design

Ahmed Egnr

Pakistan

I speak English

Embedded Systems Expert

Embedded Hardware/Firmware Design Professional having development work history targeting FPGA’s and Microcontrollers. Project lead designer , with focus on implementing DSP functions and uC/OS-ll on S...
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About this Gig

UVM Simulation framework using System verilog for functional and RTL verification of your RTL design. DUT can be in any HDL language VHDL, Verilog or SV.

do uvm simulation using systemverilog for complex hdl module or soc design
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do uvm simulation using systemverilog for complex hdl module or soc design

Platform:

Other

Expertise:

Debugging

•

SoC optimization

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