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I will design and simulate fpga in vivado
About this Gig
Need help turning a digital design into working Verilog and clear simulation results? I design, simulate and debug FPGA projects in Vivado, with MATLAB/Simulink modeling for agreed DSP tasks.
I am an electronics engineer with 3+ years of R&D experience, including a digital AGC developed in Vivado for an SDR.
Services include:
Verilog RTL modules, FSMs, counters, FIFOs and control logic
Testbenches, waveform analysis and simulation debugging
DSP blocks, fixed-point logic and MATLAB reference models
Vivado project setup and synthesis review when agreed
Every package includes source code, simulation results, documentation and setup notes. Basic covers debugging one small existing RTL module; Standard covers one new module; Premium covers up to three agreed modules and a MATLAB reference model.
Please message your specifications before ordering. Complex SDR, AGC, DSP and larger FPGA systems receive a custom quote after scope review. Hardware testing, board access, paid IP and licenses are not included. Revisions cover the agreed scope. Gallery captures are credited reference examples.
Platform:
FPGA
Expertise:
Debugging
•
Testing
•
Signal processing
My Portfolio
FAQ
What should I send before ordering?
Send the design specification, inputs/outputs, clock and reset details, target FPGA, Vivado version and deadline. For debugging, include source files, testbench and error logs. For MATLAB/Simulink, describe the algorithm and required toolbox versions. I will confirm scope and deliverables.
Do you handle MATLAB, DSP and larger FPGA projects?
Yes. I can scope MATLAB/Simulink models, fixed-point DSP, AGC and multi-module FPGA designs. Contact me first for a custom offer. Packages cover the agreed simulation work and source files; physical board testing, paid IP and software licenses require separate arrangements.
