I will design a custom riscv cpu core for your fpga or asic project

Engr Majid

Pakistan

I speak Hindi, English, Urdu

Hardware Design Engineer

I am Majid Ali, an Electrical Engineer specializing in RISC-V, SoC and ASIC design. With strong expertise in Verilog, SystemVerilog, UVM, C\C++, Python and RISC-V Assembly, I bring a solid background ...
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About this Gig

I specialize in custom RISC-V processor design, tailored to your specifications from minimal RV32I cores to pipelined architectures with additional modules.

You will get:

  • Custom RISC-V CPU architecture (Single-Cycle, Multi-Cycle, or 5-Stage Pipelined)
  • RTL design in Verilog HDL
  • Simulation testbench with waveform results (ModelSim / QuestaSim)
  • Instruction and data memory integration
  • Support for RV32I or your custom instruction set
  • Optional hazard detection, forwarding unit, and control logic
  • Modular, clean, and well-commented code
  • Detailed documentation and explanation (if needed)


Deliverables:

  • Verilog source files (.v)
  • Testbench for simulation
  • Waveform screenshots / .do files
  • PDF of processor datapath / block diagram
  • Documentation explaining modules and flow (Standard & Premium)

Why Choose Me?

  • Electrical Engineer with hands-on expertise in Computer Architecture and RTL Design
  • Practical experience with custom SoC development
  • Verified designs using industry tools like ModelSim, QuestaSim, Xilinx Vivado and FPGA boards
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design a custom riscv cpu core for your fpga or asic project
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design a custom riscv cpu core for your fpga or asic project
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design a custom riscv cpu core for your fpga or asic projectdesign a custom riscv cpu core for your fpga or asic projectdesign a custom riscv cpu core for your fpga or asic project

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