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I will design verilog and systemverilog rtl fpga modules
Hi, I'm Fahad Ahmad, an Electrical Engineer with expertise in Verilog coding, MATLAB/Python to Verilog conversion, and FPGA implementation. I deliver precise and high-quality digital design solutions,...
About this Gig
Need clean, synthesizable Verilog/SystemVerilog RTL that actually works in hardware, not just simulates?
I'm an Electrical Engineer specializing in Digital IC Design, currently training in advanced ASIC/RTL design flows. I designed and validated a full RISC-V SoC (5-stage pipelined RV32I core with branch prediction) on a Xilinx Artix-7 FPGA, hitting full timing closure with zero setup/hold violations across ~76,000 endpoints.
WHAT I BUILD:
FSMs, counters, MUXes, ALUs
UART, SPI, I2C interfaces
FIFOs, memory controllers, arbiters
Pipelined datapaths & control units
CDC-safe designs
Custom logic to your spec
WHAT YOU GET:
Clean, commented, synthesizable RTL
Simulation waveforms proving correctness
Files ready for Vivado, ISE, ModelSim, Quartus
Clear explanation of the design
TOOLS: Xilinx Vivado, Xilinx ISE, ModelSim, Intel Quartus Prime
From a single module to a full datapath/controller, I'll design it correct, synthesizable, and readable.
Send your spec before ordering so I can confirm scope and timeline.
Platform:
FPGA
FAQ
Do you provide a testbench with the Basic package?
The Basic package includes simulation waveform screenshots to prove functionality, but a formal testbench file is included starting from the Standard package. Let me know if you'd like a testbench added to Basic as a custom offer.
What tools do you use?
Xilinx Vivado, Xilinx ISE, ModelSim, and Intel Quartus Prime. I'll deliver files compatible with whichever tool you're using just tell me in advance.
Can you target a specific FPGA board (Artix-7, Nexys A7, etc.)?
Yes. I've worked with Xilinx Artix-7 and Nexys A7 boards directly. If you need board-specific constraints (XDC/UCF files) or bitstream generation, add the Vivado synthesis extra or message me first.
I only have a rough idea, not a full spec can you still help?
Yes, message me before ordering. I'll help turn your idea into a clear module spec so we're aligned on scope before work starts.
Do you do SystemVerilog verification too (UVM, constrained-random)?
Yes, that's a separate gig on my profile focused specifically on verification/UVM — check my gig list. This gig is for RTL design; the verification gig is for testbenches and coverage-driven verification.
What if my design doesn't meet timing after synthesis?
If you order the Premium package or the synthesis add-on, I'll iterate on the design to help close timing violations within the revision scope.
