I will design, debug, and optimize riscv digital systems using systemverilog and c

I am a Digital Design Engineer with 2+ years of experience in digital systems and computer architecture within the semiconductor industry.

I provide RISCV RTL development, verification, and debugging services using SystemVerilog and Verilog, aligned with industry-standard hardware development and verification flows. My work emphasizes clean, synthesizable RTL, functional accuracy, and verification-driven implementation.

I have hands-on experience working on single-cycle and pipelined processors, including 16-bit and 32-bit RISC architectures, along with UART and AMBA AXI interfaces, using Vivado-based workflows.

What I Can Do

RTL Development

• SystemVerilog / Verilog RTL implementation
• Modular and synthesizable coding style
• Datapath and control logic implementation
• Processor microarchitecture work

Verification & Debugging

• Verification test planning
• Directed testbench implementation
• RTL debugging and waveform analysis
• Functional validation and issue isolation

Protocols & Interfaces

• UART implementation and validation
• AMBA AXI protocol handling

Feel free to contact me for a discussion before placing an order.