I will help with your verilog, modelsim, and quartus fpga project

Franz V.

Philippines

I speak Tagalog, English

Excel Data Specialist, Verilog and FPGA Digital Design

Hi, I'm Franz! I offer two services: Excel data cleaning & organization, and Verilog/FPGA digital design. I'm a 3rd year Computer Engineering Technology student experienced in structured data and hard...
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About this Gig

Struggling with a Verilog assignment, FPGA project, or digital logic lab? I'll help you design, code, simulate, and debug it.

What I offer:

Verilog code writing combinational & sequential logic, FSMs, counters, timers, sequence detectors

Testbench creation and simulation in ModelSim

Quartus project setup, synthesis, and pin assignment

Debugging simulation mismatches and hardware-level issues

Clear explanations if you're learning not just handed code with no understanding

I'm a Computer Engineering Technology student with real hands-on experience building and debugging FPGA/CPLD projects including finite state machines, clock dividers, 7-segment display drivers, and sequence detectors. I've worked through actual hardware issues (faulty chips, floating pins, timing bugs) that go beyond textbook examples, so I understand both the code and the hardware behavior behind it.

Whether it's a coursework assignment, lab exercise, or small personal project, I'll make sure it works correctly and that you understand how it works.

Send me your requirements/assignment details, and I'll get started.

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help with your verilog, modelsim, and quartus fpga project
help with your verilog, modelsim, and quartus fpga project
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