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I will architect custom verilog rtl for fpga and asic synthesis

Adarsh K

India

I speak English, Hindi, German

Hardware Design Engineer and Electronics Hobbyist

Hardware Design Engineer • Working on a Ministry of Electronics and Information Technology (MeitY)-funded C2S" project— "DSP and AI Workload-Optimized Embedded RISC-V Processors" in collaboration with...
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About this Gig

VLSI & FPGA Architect | 3 year experience


Stop settling for RTL that only works in simulation. I deliver production-ready hardware and enterprise-grade VLSI implementation as a architect who understands physical silicon constraints.


Areas of Proficiency:

  • Digital Logic: Custom FSMs, Datapaths, Memory controllers.
  • AI & DSP: Neural Network Accelerators
  • ASIC Synthesis: Gate-level netlists, PPA optimization (<90nm).
  • Physical Design: Floorplanning, CTS, PnR, Layout.
  • FPGA Flow: Synthesis, bitstream, timing closure.
  • Verification: Robust testbenches & waveform debugging.

Toolstack & Skills:

  • ASIC: Synopsys Design Compiler, IC Compiler, Cadence Genus, Innovus, Virtuoso
  • FPGA: Xilinx Vivado, Intel Quartus Prime.
  • HDL/Sim: Verilog, SystemVerilog, VHDL, ModelSim.


NB: Message me before ordering to discuss your architecture and tech nodes!

  • #Verilog #FPGA #ASIC #SystemVerilog #Cadence


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architect custom verilog rtl for fpga and asic synthesis
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architect custom verilog rtl for fpga and asic synthesis
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architect custom verilog rtl for fpga and asic synthesisarchitect custom verilog rtl for fpga and asic synthesis

Platform:

FPGA

Sensors:

Temperature

•

Humidity

•

Accelerometer

•

Ultrasonic

•

Microphone

+16 more

Expertise:

Firmware development

•

Debugging

•

SoC optimization

+7 more

My Portfolio

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