I will do rtl verification and uvm testbench development for fpga and asic

Haseeb U

Pakistan

I speak Urdu, English
🔧 I’m Haseeb, a hardware design engineer with expertise in RTL design, VHDL, SystemVerilog, FPGA development, and RISC-V architecture. I work with Xilinx, Intel, and Lattice FPGAs using tools like Vi...
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About this Gig

RTL VERIFICATION ENGINEER | UVM · SystemVerilog · FPGA · ASIC


Is your RTL passing lint but failing in silicon? Bugs found late cost 10× more. I catch them at the testbench level before tapeout.


I am a professional Verification Engineer specializing in functional verification of FPGA and ASIC designs using SystemVerilog and UVM. I build verification environments that find real bugs, close real coverage, and give you confidence your RTL is correct.


WHAT I DELIVER


UVM testbench development (agent, sequencer, driver, monitor, scoreboard)

Directed & constrained-random test planning

SVA assertions protocol checkers, property specs

Coverage-driven verification (functional + code coverage)

Protocol verification: UART, SPI, I2C, AXI4, APB, AHB

Verification IP (VIP) integration

Simulation & waveform debug (ModelSim, QuestaSim, VCS, Xcelium)

Bug reports with reproducible test cases


MESSAGE ME BEFORE ORDERING

Share your RTL, protocol spec, and coverage goals I'll confirm scope and timeline.


Let's verify it right the first time.

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do rtl verification and uvm testbench development for fpga and asic
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do rtl verification and uvm testbench development for fpga and asic
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do rtl verification and uvm testbench development for fpga and asicdo rtl verification and uvm testbench development for fpga and asicdo rtl verification and uvm testbench development for fpga and asic

Platform:

FPGA

Expertise:

Firmware development

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Debugging

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SoC optimization

+4 more

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