I will provide services in digital design and verification having around 6 years exp

Have a professional experience of more than 6 years in digital logic, systems design and verification. I have strong expertise in Verilog, SystemVerilog, UVM, and Python languages and have done a lot of projects professionally and personally in them. Some of the key projects are listed below:

- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with RTL engineers to identify important verification scenarios

- Creation and execution of testplans for verification

- Architectural/Microarchitectural Verification of RISCV Debug Module implementation on proprietary ISS as well as on high end server core RTL

- Understood architectural specifications, wrote directed C and Assembly tests for functional verification and

coverage(code + functional) closure

- Ran regressions, and debugged trace failures in 22 high-end cores

- Developed post-sim and automation scripts in Python, Ruby and Bash

- Worked with our client's partner team in San Mateo, CA, USA, which involved weekly meetings

- Experience working with Mentor Graphics tools such as QuestaSim and visualizer

- SweRV Core (by Western Digital) Verification