I will do fpga rtl design in verilog and systemverilog uvm verification
FPGA Engineer for RTL Design and UVM Verification
About this Gig
Hi, I am a Digital Hardware and Verification Engineer. I design, optimize, and verify clean, synthesizable FPGA architectures based on your custom requirements, specs, or block diagrams.
I proudly welcome all international clients, corporate teams, startups, and academic students from every culture. Whether you are an industry engineer launching a hardware module or a student tackling a tough digital design assignment, I am here to fully support your project with clear communication.
What I Deliver:
Custom FPGA RTL modules and hardware IP cores using Verilog & SystemVerilog
Robust FSMs, FIFOs, counters, timers, and high-speed data pipelines
Full integration of AXI, AHB, APB, SPI, UART, and Avalon DMA protocols
Verification Testbenches and functional simulations (Layered SV & Advanced UVM 1.2)
Concurrent SystemVerilog Assertions (SVA) and functional coverage closure
Thorough RTL debugging, syntax corrections, and timing verification
Tools & Software:
Intel Quartus Prime
QuestaSim / ModelSim
Platform Designer (QSYS)
Please contact me before ordering so we can review your project specs together!
Platform:
FPGA
Sensors:
Sound & vibration
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Voltage detection
•
Camera
•
Position
Expertise:
Debugging
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SoC optimization
•
Testing
My Portfolio
FAQ
Do you accept academic assignments, university lab tasks, or custom student projects?
Yes, absolutely! I gladly accept and support university lab assignments, term projects, and custom academic tasks from students worldwide. I ensure all deliverables include clean, well-commented source code and structural simulation outputs that are easy to follow and present.
What specific FPGA hardware boards and protocols do you support?
I specialize in the Intel/Altera ecosystem, working extensively with platforms like the Terasic DE1-SoC (Cyclone V). I configure, debug, and integrate industry-standard bus protocols including AMBA AXI, AHB, APB, SPI, UART, and Avalon Memory-Mapped DMA interfaces.
Can you build a complete verification environment using UVM 1.2 from scratch?
Yes. I can architect modular, class-based SystemVerilog UVM 1.2 testbench environments complete with active agents, drivers, monitors, and self-checking scoreboards. I also write concurrent SystemVerilog Assertions (SVA) and handle constraint distributions to achieve 100% functional coverage closure

