I will help you with digital logic design, verilog and uvm

I provide professional Verilog and Digital Logic Design services with a strong foundation in real-world design verification experience. I have worked on multiple semiconductor projects involving RTL understanding, testbench bring-up, CSR verification, and protocol-based designs, which allows me to deliver logic that is not only correct in theory but reliable in simulation.

I can help you design, debug, or improve combinational and sequential logic, including FSMs, counters, registers, and datapaths. I also support Verilog testbench creation and RTL debugging with a clear, structured approach.

All code delivered under this gig is fully tested and executable on Synopsys VCS only. This ensures industry-grade simulation accuracy and avoids inconsistencies across simulators. Support for other simulators is not included unless discussed beforehand.

What I offer:

• Verilog/SV RTL coding
• Digital Logic Design (FSMs, registers, counters)
• Testbench creation & debugging (VCS)
• CSR and register-based logic
• RTL explanation and debugging

Tools: Verilog/SystemVerilog, Synopsys VCS

Focus: Correctness, clarity, and simulation reliability