I will create custom dld and fpga projects using xilinx vivado

Are you a DLD, VLSI or FPGA student and struggling with your project, assignment, or lab work?

Youre in the right place.

I will create custom DLD and FPGA projects specially designed for students and beginners. My goal is not just to deliver a project, but to make sure you understand it clearly and can explain it confidently in your viva or presentation.

I use multiple industry-standard tools, but I always keep the design simple, clear, and student-level, not complex industrial designs.

Tools & Technologies I Use:

• Logisim (for basic Digital Logic Design concepts)
• Verilog HDL
• Xilinx Vivado (FPGA design & simulation)
• Cadence Logic tools (for VLSI / logic-level design)
• IP verification using pyUVM (basic and student-friendly verification)

What You Will Get:

• Custom DLD or FPGA project based on your requirements
• Clean and easy-to-understand Verilog code
• Simulation results and outputs
• Implementation using Vivado / Logisim / Cadence (as needed)
• Simple explanation (viva & presentation friendly)
• Beginner-level IP verification using pyUVM (if required)

Even if you are a complete beginner, no problem I will guide you step by step so you can learn and present your project with confidence.