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I will asic design rtl verification and physical design
FPGA RTL Design Engineer Verilog SystemVerilog UVM RISC V
Hi! I'm Jamshaid Abbas, a passionate and detail-oriented Electrical Engineer with hands-on experience in:
✅ Circuit Design & Simulation (Proteus, Multisim, PSpice, MATLAB)
✅ RISC-V Processor Design (...
About this Gig
Are you looking for professional ASIC design, RTL verification, or physical design support?
I am an Electrical Engineer with hands-on experience in digital IC design, SystemVerilog/UVM verification, and RTL-to-GDSII design flows.
My services include:
- Specifications to synthesizable Verilog/SystemVerilog RTL
- RTL development, debugging, and optimization
- Simple directed and self-checking testbenches
- UVM testbench development, agents, sequences, drivers, monitors, and scoreboards
- SystemVerilog Assertions (SVA) and coverage analysis
- Functional simulation and regression testing
- Logic synthesis, timing and area analysis
- Physical design: floorplanning, placement, CTS, routing, and implementation reports
Tools:
Cadence Xcelium, Genus, Innovus, and suitable open-source flows using Yosys, OpenROAD, Verilator, or Icarus Verilog.
Deliverables: RTL/testbench files, scripts, simulation results, verification reports, and applicable physical design outputs.
Commercial-tool and PDK-dependent work requires appropriate licensed access.
Please contact me with your specifications before placing an order.
My Portfolio
FAQ
Can you develop both simple and UVM-based testbenches?
Yes. I can develop directed, self-checking SystemVerilog testbenches and structured UVM verification environments according to the complexity of the design.
Can you use Cadence and open-source tools?
Yes, the implementation approach can use Cadence Xcelium, Genus, Innovus, or suitable open-source alternatives. Commercial tools require valid licensed access, and physical design outputs depend on the provided technology files.
