I will design schematics, pcb layout, si pi simulation

18 years of experience in hardware research and development (HW R&D).

Extensive experience in high-speed signal processing, power noise reducing, product reliability design.

Proficient in PCB layout by PADS and Allegro.

Proficient in signal integrity and power integrity simulation, skilled use Hyperlynx and Cadence Sigrity (For PCIe Gen4 and DDR4 simulation).

Extensive experience in FPGA, skilled at Xilinx, Altera, and Lattice design.