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I will design and verify your fpga in system verilog or hls
Embedded Systems, FPGA and Software Engineer!
FPGA and embedded engineer, front-end harware oriented. I design and verify Verilog/SystemVerilog and HLS blocks, from small modules to AXI-connected accelerators and complete SoC systems for AMD/Xili...
About this Gig
Need FPGA/digital front-end design that works on real hardware, not just code that compiles? I design and verify RTL (Verilog/SystemVerilog) or build HLS designs that turn C into efficient hardware faster.
WHAT I DO
RTL: FSMs, datapaths, FIFOs, memory controllers, AXI, DSP, crypto, advanced processor architectures (OoO, VLIW), etc. are only some of them
Verification: SystemVerilog testbenches with assertions, waveforms and coverage results
HLS: C/C++ to RTL in Vitis HLS, tuned for throughput/area, cutting design time
Optimization: synthesis, timing closure, resource and power reduction
Fixes: failing simulations, synthesis errors, timing violations
TOOLS
Vivado, Vitis HLS, Quartus, ModelSim/Questa, Verilator, Python scripting on AMD/Xilinx and Intel FPGAs
HOW IT WORKS
1. You send the spec, target FPGA and constraints
2. I confirm scope and timeline
3. I deliver in milestones with updates
4. We iterate free of charge until the design meets your spec, within the initial requirements
5. You receive clean, commented source code, testbench and simulation results in a well-documented file
Not sure it fits? Message me before ordering and I'll tell you honestly if I can help.
Platform:
FPGA
FAQ
Should I choose RTL (Verilog/SystemVerilog) or HLS?
RTL gives full control over timing and area. HLS turns C/C++ into hardware faster, which suits algorithm-heavy designs. Tell me your goals and I’ll recommend the best fit.
Will my code and ideas stay confidential?
Yes. Your specs, code and results are used only for your order and never shared. If your project is sensitive, I’m happy to sign an NDA before you send anything.
Do you work with VHDL
My focus is Verilog/SystemVerilog and HLS but I design in VHDL too. If your project is VHDL-based, message me first with the details so we can check whether I’m the right fit before you order.
My project is bigger than the gig packages. What now?
Message me with your requirements and I’ll prepare a custom offer with a fixed price and delivery time that matches the real scope, so there are no surprises mid-project. Packages are only for reference purpose!
