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I will design and guide your rtl to gdsii physical design flow project
FPGA Design, Verilog, VHDL, Digital Circuit Simulation
🔬 Current ECE PhD Researcher specializing in:
• RISC-V Processor Design + UVM Verification
• Advanced DSP/ML Signal Processing (MATLAB 2025b)
• High-Density PCB (8+ layers, DDR/HDI)
• Embedded Linux ...
About this Gig
Struggling with RTL to GDSII physical design flow? As an ECE expert with hands-on Sky130 schematic-to-GDSII experience, I'll guide your VLSI project from synthesis to signoff.
SERVICES:
BASIC ($30, 2d): Flow PDF + Ubuntu setup script + 30min Q&A
STANDARD ($75, 4d): Project review + timing scripts + 1hr Zoom + 2 revisions
PREMIUM ($200, 7d): Full CTS/routing/DRC guidance + GDSII sample + IEEE report
Tools: OpenROAD, Sky130 PDK, Innovus/ICC2 basics. Perfect for VLSI interviews & M.Tech projects. Linux setups from my $100 inverter gig success!
Message for custom RTL block guidance!
FAQ
What tools do you cover?
OpenROAD/Sky130 (free, Linux-based from my inverter project), Cadence Innovus/Genus basics, Synopsys ICC2/Primetime. Ubuntu setup scripts included.
What exactly is the RTL to GDSII flow?
RTL synthesis → netlist → floorplanning → placement → CTS → routing → DRC/LVS → timing closure → GDSII signoff. Full steps in Basic PDF.
Do you do the full design and guide?
Yes—perfect for students learning VLSI interviews/M.Tech projects. Review your files, fix scripts, Zoom walkthroughs.�
