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I will design and debug verilog and systemverilog
Electrical Engineer
I am an Electrical Engineering graduate from NUST-SEECS with strong proficiency in RTL design, SystemVerilog, and FPGA synthesis. I have experience in hardware-accelerated AI inference and functional ...
About this Gig
Are you looking for clean, synthesizable and well-documented Verilog or SystemVerilog RTL for your FPGA design?
I can design, simulate, test and debug digital hardware modules based on your technical requirements.
My services include:
Combinational and sequential logic design
Finite state machines, counters, registers and multiplexers
Custom Verilog and SystemVerilog RTL modules
Testbench development and functional simulation
Debugging compilation, logic and simulation errors
Intel Quartus Prime and QuestaSim or ModelSim support
Commented source code, simulation waveforms and documentation
Why work with me?
Electrical Engineering graduate from NUST
Clear communication and properly defined deliverables
Clean, modular and understandable RTL code
Delivery according to the selected package and agreed scope
Before ordering, please provide your requirements, preferred HDL, target FPGA or device, development tool, input and output details, clock and reset requirements, and expected results.
Please contact me before placing an order, particularly for multi-module, board-specific or urgent work. For educational projects, I provide tutoring, debugging and explanatory support.
Platform:
FPGA
Expertise:
Debugging
•
Testing
•
Programming
FAQ
What information do you need before starting?
Please provide the design specification, preferred HDL, inputs and outputs, clock and reset requirements, target FPGA or board, development tool, expected behaviour and deadline. For debugging, also provide your existing code and error messages.
Which HDL languages and development tools do you support?
I work with Verilog and SystemVerilog using Intel Quartus Prime, QuestaSim and ModelSim. Please contact me before ordering if your project requires another FPGA device or development tool.
Can you debug or modify my existing RTL code?
Yes. Please provide the complete source files, compilation or simulation errors, waveform screenshots and a clear description of the expected behaviour.
Will you provide a testbench and simulation results?
Yes. Testbench development and functional simulation are included according to the selected package. Standard and Premium packages include more detailed testing and documentation.
Does this Gig include programming and testing a physical FPGA board?
This Gig primarily covers RTL source code, testbenches and simulation. Physical board implementation or testing is available only when discussed before ordering and when the requested device and tools are supported.
