I will design fpga projects using verilog vhdl,xilinx vivado,python prog data analysis
SENIOR PCB DESIGNER,Embedded Systems,Iots Development
About this Gig
I help researchers, and engineers bring their digital design ideas to life using Verilog, VHDL, Xilinx Vivado, and Python. Whether you need custom RTL logic, IP integration, or Python scripts to analyze and clean up your hardware output data, I have got you covered.
Core Expertise
- FPGA and SoC-based system design & integration
- FPGA development using Verilog, VHDL, SystemVerilog, and Chisel
- RTL coding, functional simulation, and synthesis
- Custom IP core design and integration (Vivado)
- Single-cycle, multi-cycle, and pipelined processors
- Design of FSMs, counters, ALUs, controllers, and processors
- FPGA prototyping, hardware mapping, and verification
- Embedded FPGA development.
- Creating testbenches and verification environments.
Processor & Architecture Skills
- C/C++ to assembly conversion (and reverse)
- Experience with MIPS, RISC-V, x86
Hands-On Experience With:
- Zynq Ultrascale+ MPSoC
- Zynq-7000 Series
- Spartan-3
Platform:
FPGA
Sensors:
Camera
Expertise:
SoC optimization
My Portfolio
Other Electronics Engineering Services I Offer
FAQ
Which FPGA boards do you work with?
I mainly focus on Xilinx/AMD chips (Artix-7, Kintex-7, Zynq, UltraScale+) inside Vivado, but the underlying HDL logic works across most standard boards.
Why use Python alongside FPGA development?
Python makes hardware testing much easier! It’s great for generating test vectors, reading raw output files from your board or simulator, and plotting the data so you can see if your hardware is doing what it's supposed to do.
What do you need from me to start?
A short note explaining your goals, your target chip/board model, your preferred language (Verilog or VHDL), and any block diagrams or specs you have ready.
Can you help with hardware bug fixes or existing code that isn't working?
Absolutely! Send over your current project files, block diagrams, or error logs from Vivado. I can help debug timing errors, syntax issues, or logic bugs and get your design compiling smoothly.
Will you provide the full project files upon completion?
Yes, you will receive the complete source code (.v or .vhd files), constraint files (.xdc), Vivado project archives, and any Python scripts written for data analysis or testing.
