I will write, simulate and debug riscv assembly code and isa based designs

Looking for expert help with RISC-V assembly programming, simulation, or code integration? I provide clean, efficient, and well-structured low-level development using the RISC-V instruction set.

I specialize in writing and simulating RISC-V assembly code using both lightweight educational tools like RARS and Venus, as well as professional toolchains such as the RISC-V GNU toolchain, Spike and Verilator.

Services include:

• Writing optimized and readable RISC-V assembly code (RV32I, RV64I, M, F)
• Simulating code using RARS, Venus, or Spike
• Instruction-level debugging and trace analysis
• Developing test sequences for core validation or firmware-level integration
• Creating startup routines, memory layout, and I/O interaction (if supported)
• Delivering code that runs on both educational and professional platforms

Tools Supported:

• RARS (RISC-V Assembler and Runtime Simulator)
• Venus (Web-based RISC-V simulator)
• Spike, GDB, and riscv64-unknown-elf-gcc
• Verilator (for RTL testing)
• Linux, Make, Git