I will develop fpga projects using xilinx vivado

Looking for an experienced RTL Engineer for your FPGA or ASIC project? I can help turn your hardware concept into reliable, synthesizable RTL.

I am an RTL Design Engineer at the NUST Chip Design Centre (NCDC) with professional experience in ASIC and FPGA development. I have over one year of industry experience working on H.265 (HEVC) and H.266 (VVC) video encoder hardware using Verilog and SystemVerilog.

Services include:

• Verilog and SystemVerilog RTL implementation
• FPGA and ASIC front-end development
• FSM, ALU, FIFO, UART, SPI, I2C, and memory controllers
• Testbench creation and functional verification
• RTL debugging and optimization
• Hardware accelerator development
• Digital logic and computer architecture solutions
• H.265 (HEVC) and H.266 (VVC) video codec modules

What you will receive:

• Clean and synthesizable RTL source code
• Functional simulation and verification
• Well-documented project files
• On-time delivery and responsive communication
• Revisions based on your requirements