I am a Digital Design & Verification Engineer specializing in Verilog, SystemVerilog, UVM, and RTL design. I have hands-on experience in APB, AHB, AXI, RISC-V, UART, and SoC verification. I develop pr...
Im a Digital Design and Verification Engineer with 4+ years of experience in RTL and ASIC/FPGA development. I will help you design, simulate, and verify a custom or standard RISC-V processor core (RV32I) using Verilog/SystemVerilog.
Whether you need a single-cycle, pipelined, or custom-instruction RISC-V core, Ill deliver clean, modular RTL code with a working testbench, simulation waveforms, and documentation. Ideal for students, startups, or research teams building RISC-V-based systems.