I will design rtl in verilog, systemverilog or vhdl with testbench

Need clean, working RTL for your FPGA or digital design project? I'm a Design & Verification Engineer at NUST Chip Design Center and hold RISC-V International and Xilinx FPGA certifications.

What I deliver:

- Synthesizable RTL in Verilog, SystemVerilog or VHDL

- A testbench with simulation waveforms

- State machines, counters, ALUs, FIFOs, UART/SPI/I2C and memory controllers

- Debugging and optimization of your existing code

- Short design documentation with block diagram

How it works:

1. Send your spec or existing code, target device and simulator.

2. I confirm scope, price and timeline before you order.

3. I deliver source files, testbench, waveforms and notes.

4. Revisions are included in each package.

Please message me first so I can confirm your project fits. I reply within about an hour. Need full UVM verification? See my UVM gig.