I will design debug and simulate verilog rtl projects for fpga

Muhib A

Bangladesh

I speak English

Student

Hello! I am Muhib, an undergraduate student in Electronics and Communication Engineering with 3 years experience and expertise in Digital logic design , RTL design with Verilog HDL , Design Simulati...
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About this Gig

I am an Electronics Engineering student with 3 years prior experience in Digital Logic Design, Verilog HDL, and RTL development. I have experience working on digital circuit, FSM design, counters, ALU implementation, and simulation-based hardware design projects.

My areas of expertise include:

  • RTL design using Verilog
  • Finite State Machine (FSM) design
  • Combinational and Sequential Circuit Design
  • Counters, Registers, ALU, Multiplexers
  • Testbench writing and waveform analysis
  • Simulation using ModelSim and Vivado
  • Digital circuit simulation in Proteus and Logisim
  • Debugging and optimization of Verilog code
  • FPGA-friendly digital design concepts

I am dedicated to building strong professional relationships by providing clean, organized, and understandable work with proper communication and on-time delivery.

What you will receive:

  • Verilog source code
  • Well-commented RTL modules
  • Testbenches
  • Simulation results and waveforms
  • Truth tables (if required)
  • Schematic or logic explanation
  • Proper documentation and comments

I can help with:

  • University projects
  • Lab assignments
  • Personal RTL projects
  • Beginner to intermediate digital systems

Note: Please contact me before placing an orde

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design debug and simulate verilog rtl projects for fpga
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design debug and simulate verilog rtl projects for fpgadesign debug and simulate verilog rtl projects for fpgadesign debug and simulate verilog rtl projects for fpga

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