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I will implement dsp algorithms in verilog rtl
Digital Design Engineer and Researcher
Results-driven Electronics Engineer and VLSI Architect with a proven track record in RTL microarchitecture and full-cycle automotive system development. Blends advanced R&D in neural network hardware ...
About this Gig
Senior DSP & Hardware Architect | 10 Yrs Expertise
Math is cheap in software, but expensive in hardware. Stop wasting FPGA resources on bloated IP cores. I translate complex Digital Signal Processing (DSP) algorithms into custom, high-speed physical silicon.
As a PhD-level VLSI Architect with a decade of experience, including 5 years of industrial ADAS development at TCS-EISI, I specialize in translating advanced mathematical models into optimized RTL. I design custom pipelines tailored for strict Power, Performance, and Area (PPA) constraints on FPGA and ASIC targets.
Areas of Proficiency:
- Advanced CORDIC: High-efficiency architectures, including SAM-CORDIC implementations with hardwired control units.
- Complex Filters: Spatial & frequency domain filters utilizing bit-serial and sum-of-three-terms approximations for Log-Gabor logic.
- High-Speed Datapaths: Custom MAC units, FFT pipelines, and matrix operations.
- Translation: Converting Python/MATLAB algorithms to bit-accurate Verilog/SystemVerilog.
Why Choose Me: Real-world enterprise reliability backed by advanced research.
NB: Message me with your mathematical model before ordering!
#DSP #Verilog #FPGA #CORDIC #MATLAB
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FAQ
Will you sign an NDA (Non-Disclosure Agreement)?
Yes, absolutely. I understand that architectural designs, proprietary neural network models, and DSP algorithms are highly sensitive intellectual property. I am fully open to signing an NDA before you share your project details.
What inputs do you need from me to start a design?
For the best results, I need a clear mathematical model (Python, MATLAB, or Simulink), your target technology node or FPGA family, and your strict PPA (Power, Performance, Area) or timing constraints.
Do you provide the testbench, or just the RTL code?
I provide robust, self-checking testbenches with all Standard and Premium packages. I do not believe in delivering RTL that has not been rigorously verified via waveform debugging.
Which EDA tools do you use for synthesis and physical design?
For enterprise ASIC flows, I use industry-standard Cadence tools (Genus for synthesis, Innovus for PnR). For FPGA targets, I provide full flows using Xilinx Vivado and Intel Quartus Prime. I am also highly proficient in the OpenLane open-source ecosystem.
Can you optimize my existing RTL code to meet timing?
Yes. If your current design is failing timing constraints or consuming too many resources, I can re-architect the datapath, implement pipelining, or apply bit-serial approximations to optimize it for your specific silicon target.
What technology nodes do you support for ASIC synthesis?
I specialize in synthesis and physical design for 90nm technology libraries and below, ensuring realistic, production-ready gate-level netlists.
