I will design custom fpga logic, dsp algorithms, and verilog rtl

Yes, absolutely. I understand that architectural designs, proprietary neural network models, and DSP algorithms are highly sensitive intellectual property. I am fully open to signing an NDA before you share your project details.

For the best results, I need a clear mathematical model (Python, MATLAB, or Simulink), your target technology node or FPGA family, and your strict PPA (Power, Performance, Area) or timing constraints.

I provide robust, self-checking testbenches with all Standard and Premium packages. I do not believe in delivering RTL that has not been rigorously verified via waveform debugging.

For enterprise ASIC flows, I use industry-standard Cadence tools (Genus for synthesis, Innovus for PnR). For FPGA targets, I provide full flows using Xilinx Vivado and Intel Quartus Prime. I am also highly proficient in the OpenLane open-source ecosystem.

Yes. If your current design is failing timing constraints or consuming too many resources, I can re-architect the datapath, implement pipelining, or apply bit-serial approximations to optimize it for your specific silicon target.

I specialize in synthesis and physical design for 90nm technology libraries and below, ensuring realistic, production-ready gate-level netlists.