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I will develop and verify rtl designs using verilog, systemverilog and uvm

Osama

Pakistan

I speak Urdu, Pashto, English
FPGA and RTL Design Engineer with hands-on experience in Xilinx Zynq RFSoCs, RISC-V processor design, and SystemVerilog verification. I've built multicycle and pipelined processors from scratch, worke...
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About this Gig

Are you looking for a reliable engineer to design, verify, or debug your RTL and FPGA projects? You're in the right place.

I specialize in RTL design and functional verification using SystemVerilog and UVM. With hands-on experience from industry roles and academic research, I deliver production-quality work not just code that simulates.

What I can do for you:

  • Write and verify RTL designs in Verilog / SystemVerilog
  • Build layered UVM testbenches (driver, monitor, scoreboard, coverage)
  • Verify SPI, UART, AXI, Wishbone interfaces
  • FPGA implementation on Xilinx Vivado / Quartus
  • Timing analysis, synthesis, and debugging
  • Simulation using QuestaSim or Cadence Xcelium

I have designed multicycle and pipelined RISC-V processors, verified SPI cores with full UVM environments, and worked with Xilinx Zynq RFSoCs in professional RF systems. I am currently a Research Affiliate at GIST University, South Korea.

Clear communication, on-time delivery, and clean documented code every time. Message me before ordering so we can discuss your exact requirements.

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develop and verify rtl designs using verilog, systemverilog and uvm
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develop and verify rtl designs using verilog, systemverilog and uvm

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