I will design and debug verilog or vhdl rtl with testbench

Parth

India

I speak English

FPGA RTL Engineer Verilog VHDL Testbench Debugging C Cpp Python

I am a Master’s graduate in Integrated Circuits and Systems with hands-on experience in FPGA and digital design. I work with Verilog, VHDL, C, C++, and Python to build and debug reliable solutions. I ...
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About this Gig

I can design, debug, and verify RTL modules with clean and synthesizable code. Whether you need help fixing simulation errors or building a module from scratch, I can support you.


Services include:

Verilog or VHDL RTL design

FSM, counters, UART, SPI basics

Testbench creation

Simulation debugging

Waveform verification

Code optimization


I am a Masters graduate in Integrated Circuits and Systems with hands-on experience in digital design.

Please message me before placing an order to discuss your requirements clearly.

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design and debug verilog or vhdl rtl with testbench
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design and debug verilog or vhdl rtl with testbench

Platform:

FPGA

Expertise:

SoC optimization

•

Microcontrollers

•

Programming

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