I will do rtl design and verification using verilog, systemverilog

Poorna

India

I speak English
I'm a freelance VLSI engineer with experience in digital design, RTL coding, and functional verification for ASIC and FPGA projects. I specialize in end-to-end hardware development, from architecture ...
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About this Gig

Are you working on an ASIC or FPGA project and need help with RTL design or verification?

You're in the right place!


I offer professional RTL design and testbench development using Verilog/SystemVerilog for basic to advanced hardware modules. Whether you're a student, researcher, or engineer, I can help you get your design simulated, verified, and ready.


Basic RTL Design & Testbench

  • Simple RTL module (1-level logic)
  • Basic testbench structure
  • Input stimulus & monitoring
  • Waveform output
  • Verilog/SystemVerilog
  • Up to 1 module


Standard and Premium

Multi-Level RTL Design & Testbench

  • Hierarchical/multi-level design
  • Complete testbench structure
  • Input/output stimulus & checks
  • Waveform generation and observations
  • Design structure with clean code and modularity
  • Basic assertions included
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do rtl design and verification using verilog, systemverilog
do rtl design and verification using verilog, systemverilog
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do rtl design and verification using verilog, systemverilogdo rtl design and verification using verilog, systemverilogdo rtl design and verification using verilog, systemverilogdo rtl design and verification using verilog, systemverilog

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