I will design synthesizable rtl and systemverilog uvm testbench

Muhammad Ramish

Pakistan

I speak English, Urdu

ASIC Digital Design and Verification Engineer

I'm a digital design and verification engineer with 3+ years of ASIC and FPGA experience. I mostly work in SystemVerilog, with Python and C++ for reference models and scripting. I've used Synopsys VCS...
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About this Gig

I'm a digital design and verification engineer with 3+ years of hands-on ASIC and FPGA work. Most of my day is SystemVerilog, and I use Python and C++ for reference models, scripts and checking tools.


What I can help with:

- SystemVerilog rtl design and self-checking tests

- Verifying bus interfaces, especially AXI4

- Processor and RISC-V verification using open-source test suites

- RTL design and cleanup, including lint fixes

- Python models to check behaviour before you commit to RTL

- Makefile flows and file lists for simulation


Tools: Synopsys VCS, Cadence Xcelium, Xilinx Vivado, and MATLAB/Simulink when a model is needed.


How I work: send me your spec and RTL before ordering. I'll read them and tell you what I can realistically deliver and how long it will take. Deliveries include rtl design, testbench, run scripts, design documentation and a short note on what was tested and what wasn't.

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design synthesizable rtl and systemverilog uvm testbench
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design synthesizable rtl and systemverilog uvm testbenchdesign synthesizable rtl and systemverilog uvm testbenchdesign synthesizable rtl and systemverilog uvm testbench

Platform:

FPGA

Expertise:

Firmware development

•

Debugging

•

SoC optimization

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