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I will design and simulate your verilog rtl module with testbench
Electronics Engineer with expertise in RTL Circuit Sim and PCB Design
Electronics engineering student (Instrumentation & Controls, NSUT) with hands-on experience in RTL design (Verilog: FIFO, FSM), analog circuit simulation (LTspice, QUCS — RC, Op-Amp, filter circuits),...
About this Gig
I'll help you design, debug, or verify small-to-medium digital logic modules in Verilog FIFOs, FSMs, counters, ALUs, and similar RTL blocks. I'll write clean, synthesizable RTL along with a self-checking testbench in Icarus Verilog, and share waveform screenshots (GTKWave) showing correct functional behavior.
Good for: coursework help, small FPGA projects, debugging existing RTL that isn't behaving as expected, or verifying your design against a spec.
What you'll get: RTL file(s), testbench, waveform output, and a short write-up explaining what was verified.
Platform:
Other
Sensors:
Other
Expertise:
Debugging
•
Testing
•
Programming
FAQ
Can you debug my existing Verilog code instead of writing new code?
Yes — send me your code and a description of the issue, and I'll debug it, explain the root cause, and share corrected code with a testbench proving the fix.
Can you help with my college/university assignment?
Yes, I regularly help with coursework-level Verilog assignments — FIFOs, FSMs, counters, ALUs, and similar digital logic modules.
