I will design and simulate risc v processors in verilog vhdl

Saad Afridi

Pakistan

I speak English

AI Computer Architecture Engineer

I am a Computer Engineering student and AI Computer Architecture Intern at Logical Silicon Inc. I specialize in computer architecture, RTL design, and AI hardware acceleration, with expertise in Veril...
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About this Gig

truggling with a Verilog, VHDL, or RISC-V processor assignment or project? I'll design, simulate, and document it for you clean, working, and delivered fast.

I'm a Computer Engineering student (GIKI) currently working as an AI Computer Architecture Engineer, with hands-on experience building RISC-V processors from scratch: single-cycle, 5-stage pipelined, and custom instruction-set extensions (CFU/MAC units) on real FPGA hardware (Xilinx Vivado, Nexys A7).

What I can help with:

  • Verilog / VHDL modules (ALU, FSM, decoder, counter, etc.)
  • RISC-V processor design (single-cycle, pipelined, custom ISA)
  • Testbenches + simulation waveforms (Vivado, Verilator)
  • University lab assignments & FYP/capstone support
  • Clear documentation so you understand your own code

Why work with me:

  • Fast delivery (2 days on Basic)
  • Real FPGA + industry experience, not just theory
  • Clean, well-commented code you can explain in your viva/demo

Message me your requirements before ordering so I can confirm scope and timeline.

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design and simulate risc v processors in verilog vhdl
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design and simulate risc v processors in verilog vhdl
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Control type:

Other

Device brands:

Other

Programming language:

C/C++

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MATLAB

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Python

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Other

Software:

Other

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