I offer proven expertise in RTL design and Verilog, delivering robust, well-documented solutions for custom processors, RISC-V architectures, and complex FPGA systems.
Core Services:
- Development: Custom FPGA and RTL design, coding, and debugging.
- Verification: Testbench creation and thorough simulation using ModelSim.
- Implementation: FPGA synthesis, timing analysis, and board bring-up via UCF constraints.
Project Expertise:
- Custom CPUs & RISC-V cores (single-cycle to pipelined).
- ALUs, FSMs, counters, and complex datapath/control logic.
- UART, FIFO/LIFO buffers, and memory design.
- Algorithm-level RTL translation for academic research or industrial use.
Tools & Platforms:
- Hardware: Xilinx FPGAs.
- Software: ModelSim, Intel Quartus, Proteus.
- Deliverables: Clean, modular, and highly scalable RTL with proper hierarchy and documentation.