I will design and implement fpga project using verilog and vhdl

Hello,

I am an FPGA and RTL Design Engineer with 3 years of industrial experience building and deploying complet digital systems on Xilinx and Altera platforms including Kintex UltraScale+, Nexys A7, ZedBoard, and Spartan-6.

What I will design and deliver for you:

RTL Design and Implementation

• Verilog and VHDL module design
• Parameterized and reusable architecture
• Pipelining and timing optimization
• Clock domain crossing and CDC handling
• Resources optimization
• Floating point fast adders mutiplers

Protocol and Interface Implementation

• UART, SPI,MIPI CSI-2,PCIE
• AXI4 and AXI-Lite
• DMA based data movement

Verification and Testing

• Testbench development
• Simulation waveforms and results
• Python co-simulation and golden model validation

FPGA Platforms I work on:

• Xilinx: Kintex UltraScale+, Nexys A7, ZedBoard, Spartan-6
• Altera: DE1-SoC
• Tools: Vivado, Quartus Prime, Xilinx ISE

Why work with me:

Client satisfaction is my first Priority 

• Clean, documented, and synthesizable RTL
• Timing closure guaranteed
• Revisions until you are satisfied

Message me before ordering so we can discuss your requirements and finalize the best plan for your project