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I will do asic design, rtl development, vhdl verilog coding and fpga development
ASIC Design RTL Verification Verilog and SystemVerilog Engineer
I specialize in ASIC design, RTL development, digital logic design, and hardware verification for semiconductor and embedded computing projects. My services cover Verilog, SystemVerilog, VHDL, RTL sim...
About this Gig
ASIC design, RTL development, digital logic design, and hardware verification expert for your semiconductor or embedded computing projects. I deliver production-ready Verilog, SystemVerilog, and VHDL code optimized for performance, area, and power.
MY SERVICE ARE:
- RTL code development in Verilog, SystemVerilog, and VHDL.
- Custom digital IP core architecture and design.
- Finite State Machine (FSM) optimization.
- FPGA prototyping on AMD Xilinx and Intel Altera.
- RTL simulation using ModelSim, Questa, and Xcelium.
- Functional verification environment development.
- UVM testbench component creation.
- SystemVerilog Assertions (SVA) writing.
- Synthesis support and netlist generation.
- Timing closure and resolving setup/hold violations.
- Bus protocol integration for AXI4, Avalon, and APB.
- Peripheral controller design for SPI, I2C, and UART.
- DSP block hardware implementation.
- Memory interface integration for FIFO and SRAM.
- Legacy code conversion between VHDL and Verilog.
Supported EDA Tools
- AMD Xilinx Vivado / Intel Quartus Prime
- Siemens ModelSim / Questa Sim
- Synopsys Design Compiler / Cadence Xcelium
Please contact me before placing an order
Control type:
PLC
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SCADA
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Other
Programming language:
C/C++
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MATLAB
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Python
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Other
Software:
Matlab
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Other
FAQ
What inputs do you need to start my digital design project?
Please provide your architectural specifications, block diagrams, timing requirements, or functional descriptions. For FPGA prototyping, specify the target board or FPGA part number.
Do you write clean, synthesis-ready code?
Yes. All RTL code in Verilog, VHDL, or SystemVerilog follows industry-standard guidelines and is fully optimized for area, power, and timing closure.
Which EDA tools and IDEs do you support?
I support AMD Xilinx Vivado, Intel Quartus Prime, Siemens ModelSim/Questa Sim, Synopsys Design Compiler, and Cadence Xcelium.
Can you build a verification environment for my existing RTL?
Yes. I develop robust functional verification environments using SystemVerilog Assertions (SVA) and structured UVM or self-checking testbenches.
Do you help resolve setup and hold timing violations?
Yes. I provide synthesis support and timing closure services to fix routing bottlenecks, establish proper constraints, and ensure your design runs at target clock frequencies.
Can you convert code from VHDL to Verilog or vice versa?
Yes. I can port legacy codebase architectures between VHDL, Verilog, and SystemVerilog while maintaining functional accuracy.
