I will design verilog or system verilog modules for your fpga or rtl project


About this gig
Need Verilog or SystemVerilog code for a class project, personal FPGA build, or RTL assignment? I'll write synthesizable, well-structured HDL code with testbenches that actually simulate and synthesize cleanly.
I've worked with Xilinx Vivado targeting real FPGA hardware not just simulation so I understand the difference between code that looks right and code that works on silicon.
What I can help with:
- Combinational and sequential logic design
- FSM implementation and optimization
- ALU, counters, shift registers, memory modules
- UART, SPI, I2C controllers in Verilog
- Testbench writing and simulation (ModelSim, Vivado)
- Xilinx FPGA targeting (Basys3, Genesys-2)
Every delivery includes .v or .sv files, a testbench, and a brief explanation of the design. Not sure if your project fits? Message me first I'll give you a straight answer.
Get to know Joel James
Python, Embedded C and Verilog developer for hire
- FromIndia
- Member sinceSep 2025
- Avg. response time8 hours
- Last delivery2 months
Languages
English
FAQ
What information do you need to get started?
Just describe the module you need — inputs, outputs, and what it should do. A block diagram or truth table helps but isn't required.
Will the code synthesize on my FPGA board?
Yes — I write synthesizable RTL, not just simulation code. Tell me your board and target tool (Vivado, Quartus) and I'll make sure it's compatible.
Can you help fix or improve existing Verilog code?
Yes — send me your code and describe the issue. I can debug, optimize, or add new functionality to existing designs.
Do you provide simulation results or waveforms?
Yes — for Standard and Premium packages I include testbench simulation results so you can verify the design before deploying to hardware.

