Browse categories
Explore
Fiverr Pro
English
$
USD
I will write verilog or systemverilog rtl with testbench and simulation
Joel James
About this gig
Need working Verilog or SystemVerilog without the debugging headache? I write clean, synthesizable RTL and verify it with a self-checking testbench before delivery.
What you get:
- RTL module(s) to your spec: FSMs, counters, shift registers, FIFOs, UART / SPI / I2C controllers, ALUs, simple pipelines
- A self-checking testbench that reports PASS or FAIL
- Simulation waveforms (.vcd) you can open in GTKWave
- Commented code and a short README with the port list and timing notes
Simulation is done with Icarus Verilog and GTKWave. Tell me your target FPGA or tool flow and I'll write the code to suit it, and I'll say plainly what I've verified in simulation and what I haven't run on hardware.
I can also debug existing code, fix simulation mismatches, or turn a spec or block diagram into RTL. Please include the spec, the interface signals and any timing requirements when you message me.
I build and explain designs for learning and real projects. I don't take graded exams.
Get to know Joel James
Joel James
Python, Embedded C and Verilog developer for hire
- FromIndia
- Member sinceSep 2025
- Last delivery6 months
Languages
English
Hi, I'm Joel — an Electronics & CS engineering student with hands-on experience in Python automation, embedded systems, and FPGA/Verilog design.
I've built web scrapers, data processing scripts, Arduino and ESP32 IoT projects, and Verilog modules for real hardware targets. I know what it's like to be a student working on tight deadlines — so I keep my communication clear and my deliverables clean.
Whether you need a Python script that saves you hours, an embedded project done right, or Verilog code that actually synthesizes — I've got you covered.
Let's build something.
FAQ
What information do you need to get started?
Just describe the module you need: inputs, outputs, and what it should do. A block diagram or truth table helps but isn't required. If you have a target FPGA board or tool flow, mention it too.
Will the code synthesize on my FPGA board?
Yes, I write synthesizable RTL and follow standard coding practice for FPGA flows. Tell me your board and tool (Vivado, Quartus, etc.) and I'll write the code to suit it. I verify everything in simulation with a self-checking testbench, and I'll tell you plainly if something hasn't been run through
Can you help fix or improve existing Verilog code?
Yes. Send me your code and describe the issue, such as a simulation mismatch, a latch warning or a timing problem. I can debug, optimise, or add new functionality to existing designs. Message me first and I'll give you a quote.
Do you provide simulation results or waveforms?
Yes. Every package includes a self-checking testbench that reports PASS or FAIL. Standard and Premium also include the simulation waveform file (.vcd), which you can open in GTKWave, so you can verify the design before deploying to hardware.
