I will design verilog or system verilog modules for your fpga or rtl project

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Joel James

About this gig

Need Verilog or SystemVerilog code for a class project, personal FPGA build, or RTL assignment? I'll write synthesizable, well-structured HDL code with testbenches that actually simulate and synthesize cleanly.

I've worked with Xilinx Vivado targeting real FPGA hardware not just simulation so I understand the difference between code that looks right and code that works on silicon.

What I can help with:

  • Combinational and sequential logic design
  • FSM implementation and optimization
  • ALU, counters, shift registers, memory modules
  • UART, SPI, I2C controllers in Verilog
  • Testbench writing and simulation (ModelSim, Vivado)
  • Xilinx FPGA targeting (Basys3, Genesys-2)

Every delivery includes .v or .sv files, a testbench, and a brief explanation of the design. Not sure if your project fits? Message me first I'll give you a straight answer.

Get to know Joel James

Joel James

Python, Embedded C and Verilog developer for hire

5.0(1)
  • FromIndia
  • Member sinceSep 2025
  • Avg. response time8 hours
  • Last delivery2 months
  • Languages

    English
Hi, I'm Joel — an Electronics & CS engineering student with hands-on experience in Python automation, embedded systems, and FPGA/Verilog design. I've built web scrapers, data processing scripts, Arduino and ESP32 IoT projects, and Verilog modules for real hardware targets. I know what it's like to be a student working on tight deadlines — so I keep my communication clear and my deliverables clean. Whether you need a Python script that saves you hours, an embedded project done right, or Verilog code that actually synthesizes — I've got you covered. Let's build something.