I will verilog systemverilog rtl fpga and asic design

India

I speak English, Hindi, Kannada, Malayalam

VLSI and FPGA Engineer: RTL to GDS, RTL Design, DSP, RISCV

I am an IIT M.Tech graduate in VLSI with 10+ years of experience in VLSI design, FPGA development, RTL implementation and semiconductor workflows. Skilled in Verilog/SystemVerilog, FPGA, DSP, RISC-V, ...
About this Gig

Need help in Verilog, SystemVerilog, FPGA or RTL design projects?


I provide support for RTL coding, FPGA implementation, simulation, debugging, waveform analysis, DSP architectures, AI/ML/DL accelerators, RISC V projects and ASIC related workflows. Services include Verilog/SystemVerilog development, FPGA design using Xilinx tools, architecture understanding, technical documentation and implementation guidance.


I focus on clean RTL design, practical engineering workflow and clear technical communication. Please contact before placing order for complex or research oriented projects.

Platform:

FPGA

Sensors:

Other

Expertise:

SoC optimization

Signal processing

Other