I will design high performance fpga hardware accelerators and verilog rtl

High-Performance FPGA Design & AI Acceleration

Are you struggling with high latency in your AI models? Or perhaps you're facing timing closure issues in your current RTL? I specialize in transforming complex algorithms into optimized hardware architectures.

What I offer:

• Custom RTL Design: Clean, synthesizable Verilog/SystemVerilog tailored for Xilinx (Vivado/ISE) or Intel (Quartus).
• AI/ML on Edge: I specialize in hardware accelerators for CNNs, YOLO, and DSP algorithms, optimizing for both throughput and resource utilization (LUTs/DSPs).
• Verification: Robust testbenches with self-checking mechanisms to ensure "First-Time-Right" hardware.
• AXI Interfacing: Expertise in AXI4, AXI-Lite, and AXI-Stream for seamless SoC integration (Zynq/UltraScale+).

Tools I Use:

• Xilinx Vivado / ISE / Vitis
• ModelSim / QuestaSim
• MATLAB/Simulink

Deliverables:

1. Fully commented RTL Source Code.
2. Testbench & Simulation Waveforms.
3. Resource Utilization & Timing Reports.
4. (Optional) Python/C++ drivers for hardware testing.

Please contact me before placing an order to discuss your architecture and constraints!